A Core Compute Die CCD is a silicon chiplet inside modern AMD processors that houses the actual processing cores, their individual L2 caches, and a shared L3 cache. It acts as the primary computational engine of the CPU, separated physically from input/output controllers.
AMD introduced the CCD architecture to break away from traditional single-piece monolithic chip designs. By manufacturing smaller individual dies and connecting them on a single substrate, production yields improve, and manufacturing costs drop significantly. CCDs are prominently used in AMD Ryzen desktop processors and EPYC server processors.
A CCD is a physical silicon chiplet containing CPU cores and cache memory.
It separates processing logic from input/output (I/O) logic to maximize manufacturing efficiency.
Each CCD contains one or two Core Complex CCX units depending on the CPU generation.
Multiple CCDs can be combined on a single CPU package to scale core counts easily.
The journey of the CCD reflects AMD's shift toward modular chiplet design across different Zen architecture generations.
In the Zen 2 architecture, a CCD contained two separate Core Complexes CCXs. Each CCX had 4 cores and an isolated pool of L3 cache. This meant cores on the same CCD had to travel across a bus to talk to the other half of the chiplet. Zen 3 fixed this by unifying the CCD into a single CCX containing 8 cores and a massive shared pool of L3 cache, drastically reducing latency.
With Zen 4, the CCD transitioned to advanced 5nm process nodes, introducing support for DDR5 memory and PCIe Gen 5 through an updated IO die. Zen 5 refines this further with tighter power efficiency and architectural layouts optimized for artificial intelligence and AVX 512 execution workloads.
A CCD functions as the raw muscle of the processor, but it does not work alone. It relies on a separate companion chip called the Input Output Die IOD.
The cores inside the CCD handle calculations, data processing, and logic operations. When a core needs to read from system RAM or talk to a graphics card, it sends a request out of the CCD. The data travels across high-speed interconnect pathways called Infinity Fabric, passes into the IO die, and routes to the appropriate component.
Silicon Efficiency: Small square dies are less likely to suffer from manufacturing defects compared to large monolithic chips.
Cache Proximity: Cores inside a single CCD enjoy ultra-low-latency access to the pooled L3 cache sitting right beside them.
Thermal Density: Because multiple cores are packed tightly into a tiny silicon footprint, CCDs generate highly concentrated thermal hotspots that require quality cooling systems.
| Feature | CCD Chiplet Architecture | Monolithic Architecture |
|---|---|---|
| Structure | Multiple specialized dies on one substrate | One single piece of silicon for all functions |
| Manufacturing Cost | Lower for high core counts | Extremely high for large multi core chips |
| Defect Vulnerability | Low individual dies can be discarded | High a single defect can ruin the whole chip |
| Internal Latency | Higher when communicating between dies | Lower across the entire processor |
Scalability: AMD can build an 8-core mainstream CPU with one CCD or a 16-core enthusiast CPU simply by dropping a second CCD onto the substrate.
Cost Effectiveness: Manufacturing smaller dies increases the number of usable chips per silicon wafer, saving money.
Mixed Process Nodes: The compute-heavy CCD can use expensive cutting-edge silicon processes while the IO die uses cheaper, mature silicon nodes.
Inter-Die Latency: If a core on CCD 0 needs to share data with a core on CCD 1, the data must travel through the IO die, causing a minor latency penalty.
Asymmetric Performance: In dual CCD mainstream processors like the Ryzen 9 series, Windows scheduling must ensure games run entirely within a single CCD to prevent performance drops caused by cross-die communication.
CCX Core Complex: The internal cluster of cores and shared L3 cache inside a CCD.
IO Die IOD: The central hub chiplet that handles memory channels, PCIe lanes, and peripheral connections.
Infinity Fabric: The proprietary high-speed interconnect system AMD uses to link CCDs to the IO die.